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EN0-001 – ARM Accredited Engineer

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Showing 7–9 of 15 questions

Question 7

When an ARMv7-A MPCore system is in SMP mode, which of the following TWO operations can the processor handle automatically? (Choose two)

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    Coherency management between all L1 data caches
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    Broadcast of some inner-shared cache and TLB maintenance operations
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    Broadcast of some outer-shared cache and TLB maintenance operations
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    Coherency management between all L1 instruction caches
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    Coherency management between all external caches
Question 8

When debugging an embedded Linux system, which one of the following techniques can be used to halt a single user thread, while allowing other threads to continue to run during the debug process?

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    Halting a single user thread in an embedded Linux system is not possible
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    Use the Linux kernel printk() function to output messages to the console
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    Connect a Linux-aware JTAG debugger to the target, which allows single-stepping of the code
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    Connect a debugger running on an external host device to an instance of gdbserver running on the target, using Ethernet
Question 9

In an ARMv7-A processor with Security Extensions, which of the following mechanisms best describes the way Secure memory is protected from access by software running in a Non-secure privileged mode?

Select an option, then click Submit answer.

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    The memory system has visibility of the security status of all accesses, and will reject all Non-secure accesses to Secure memory
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    Secure memory contents are encrypted, and cannot be decrypted by Non-secure software
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    The level 2 cache controller blocks all accesses to Secure memory when the SCR.NS bit of the processor is set
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    The MMU generates an abort on accesses to Secure memory performed by Non-secure software