Free EN0-001 – ARM Accredited Engineer Practice Test Question

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  Processor reset

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  Switching from ARM to Thumb state

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  Changing the access permissions of a page

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  Executing a Data Memory Barrier instruction

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  Loading data from an unaligned memory address
  

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  Thumb is a hybrid 16/32-bit instruction set

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  No Thumb instructions can be conditionally executed

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  Thumb code is always slower than the equivalent ARM code

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  Some routines take more instructions in Thumb code than in the equivalent ARM code

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  The Thumb instruction set can access the Advanced SIMD "NEON" instructions

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  Thumb code is always more power-efficient than equivalent ARM code
  

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  The time spent waiting for I/O operations

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  The time taken to download the program via the debugger

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  The time taken for memory accesses

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  The time taken for the CPU to execute instructions

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  The time taken to compile the source code

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  The time taken to perform instruction tracing
  

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  Interrupt from a private peripheral to a processor

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  Interrupt from a processor to a private peripheral

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  Interrupt from a shared peripheral to a processor

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  Interrupt from a processor to a shared peripheral

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  Interrupt from a private peripheral to a shared peripheral

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  Interrupt from a shared peripheral to a private peripheral
  

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  Use a do/while loop instead of a for loop

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  Change the type of sum to be an unsigned short

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  Change the type of i to be an unsigned int

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  Use signed variables instead of unsigned variables

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  Declare sum as a global variable
  

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  ROM

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  Heap

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  Cache

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  Registers

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  Stack
  

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  Coherency management between all L1 data caches

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  Broadcast of some inner-shared cache and TLB maintenance operations

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  Broadcast of some outer-shared cache and TLB maintenance operations

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  Coherency management between all L1 instruction caches

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  Coherency management between all external caches
  

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  Halting a single user thread in an embedded Linux system is not possible

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  Use the Linux kernel printk() function to output messages to the console

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  Connect a Linux-aware JTAG debugger to the target, which allows single-stepping of the code

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  Connect a debugger running on an external host device to an instance of gdbserver running on the target, using Ethernet
  

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  The memory system has visibility of the security status of all accesses, and will reject all Non-secure accesses to Secure memory

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  Secure memory contents are encrypted, and cannot be decrypted by Non-secure software

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  The level 2 cache controller blocks all accesses to Secure memory when the SCR.NS bit of the processor is set

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  The MMU generates an abort on accesses to Secure memory performed by Non-secure software
  

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  A simpler branch instruction can be used.

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  Decrementing variables uses less power than incrementing them.

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  The decrement and branch operations can be encoded as a single instruction.

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  The loop termination condition check can be integrated into the subtract operation.
  

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  It is fetched.

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  It is decoded.

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  It is executed.

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  It writes back its results.
  

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  Both IRQs and FIQs are enabled

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  Both IRQs and FIQs are disabled

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  IRQs are disabled and FIQs are enabled

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  IRQs are enabled and FIQs are disabled
  

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  a->s0; b->d0; c->s1

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  a->s0; b->d1; c->s1

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  a->d0; b->d1; c->d2

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  a->s0; b->d1; c-> s2
  

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  Disabling inlining.

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  Never passing more than four parameters in function calls.

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  Declaring automatic variables as "packed".

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  Configuring the compiler to optimize for space.
  

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  Cortex-M0+

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  Cortex-M4

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  Cortex-R4

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  Cortex-A15