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EN0-001 – ARM Accredited Engineer

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Showing 1–3 of 15 questions

Question 1

In a Cortex-A processor, after which TWO of these events is a cache maintenance operation required to ensure reliable code execution? (Choose two)

Select all that apply, then click Submit answer.

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    Processor reset
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    Switching from ARM to Thumb state
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    Changing the access permissions of a page
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    Executing a Data Memory Barrier instruction
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    Loading data from an unaligned memory address
Question 2

Many ARM cores provide two instruction sets, ARM and Thumb. Which THREE of the following statements apply to the Thumb instruction set implemented for the ARMv7-A architecture? (Choose three)

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    Thumb is a hybrid 16/32-bit instruction set
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    No Thumb instructions can be conditionally executed
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    Thumb code is always slower than the equivalent ARM code
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    Some routines take more instructions in Thumb code than in the equivalent ARM code
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    The Thumb instruction set can access the Advanced SIMD "NEON" instructions
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    Thumb code is always more power-efficient than equivalent ARM code
Question 3

In an experiment, the time taken for an application to complete a given task is measured using a stopwatch. Which THREE of the following make up the total time? (Choose three)

Select all that apply, then click Submit answer.

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    The time spent waiting for I/O operations
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    The time taken to download the program via the debugger
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    The time taken for memory accesses
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    The time taken for the CPU to execute instructions
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    The time taken to compile the source code
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    The time taken to perform instruction tracing